Exemplary applications thereof include binary counters and synchronous frequency dividers. Considering binary counters, a one-bit counter has an input and n outputs which are the encoded form of the number of pulses that have been applied to the input from the initial time when the counter is reset. Therefore, the output states are 0, 1, 2, . . . , m, and 0, 1, 2, . . . , m. The n outputs allow 2.sup.n different numbers to be encoded where m&lt;2.sup.n -1.
For a synchronous binary counter, the outputs are the numbers 0, 1 , . . . , 2.sup.n -1 expressed in the binary system. The transfer function is [C]=[C]+1 (mod 2.sup.n). This function has the following equations: EQU y.sub.0 =y.sub.0 XOR1 EQU y.sub.i =y.sub.i XOR y.sub.i-1 XOR y.sub.i-2. . . XOR with y.sub.0 i=1, 2, . . . , n-1,
and where XOR is the exclusive OR logic operation.
These equations suggest using a toggle flip-flop cell. The toggle flip-flop changes over when T=1, otherwise the FFT cell would store the previous output value.
As shown in FIG. 1 of the drawings, and as well known to skilled persons in the art, a toggle flip-flop for use in monolithically integrated circuit devices generally comprises a flip-flop of the D-type (FFD) 2 and an XOR logic gate circuit 4. The XOR circuit has its output terminal connected to the input terminal of FFD and an input terminal connected to the output terminal of the flip-flop. The other input terminal is the T input of the resultant flip-flop of the T-type. Let D be the input data of FFD 2 and Q the output data, the equation at the input becomes: EQU D=(T) XOR (Q),
which is of the same type as the equations for the binary counter.
The most commonly adopted constructions for a flip-flop of the T-type are as detailed herein below.
One construction provides standard logic gates 6, 8, 10 for the XOR input gate 4, and a cascade-connected flip-flop 2 of the D-type. This solution has an advantage in that it has good driving capability. But where NAND gates are used, for example, a large number of transistors (16=3 NANDs+2 NOTs) and complementary input signals (T, NT, Q, NQ) become necessary, as shown in FIG. 2 of the drawings.
A similar construction, retaining the valuable driving features of the former, may be implemented using a complex gate of the type shown in FIG. 3 for the XOR gate in order to use fewer transistors (10=complex gate) and avoid the need for complementary signals.
Using transfer gates as shown in FIG. 4 of the drawings may further reduce the number of transistors used (8=2 transfer gates+NOTs), but at the cost of a lower driving capability than that of the previous solutions, and requiring complementary input signals. The construction shown in FIG. 4 is preferred where savings in integration area are a condition.